During the manufacture of a semiconductor device, features are commonly patterned using optical lithography (photolithography). An exemplary photolithographic method and formation of a digit line contact is depicted in FIGS. 1-4. FIG. 1 depicts a conductively-doped diffusion region 10 within a semiconductor wafer 12, and a dielectric layer 14 such as borophosphosilicate glass (BPSG) formed over the wafer surface. A photoresist (resist) layer 16 is formed on the dielectric layer 14, then the photoresist layer is exposed and the exposed portion is removed to result in the structure of FIG. 1. The dielectric layer is etched using the resist 16 as a mask to form an opening 20 in the dielectric layer 14 to expose region 10 within semiconductor wafer 12 to result in the structure of FIG. 2. Next, the photoresist layer is removed and at least one metal layer 30 is deposited over the surface of the dielectric layer 14 and within the opening to result in the structure of FIG. 3. Finally, the metal layer 30 is planarized using mechanical polishing such as chemical mechanical polishing (CMP) to remove the metal layer 30 from the upper surface of the dielectric layer 14 and to form a digit line contact plug 32. A conductive line 40 is formed as depicted in FIG. 4 to electrically connect the plug 32 with peripheral circuitry (not depicted).
A continual design goal during the manufacture of semiconductor devices is to produce smaller features. One limit to this goal is the deficiencies in optical lithography which restrict the minimum feature size. This minimum for feature sizes results from various optical properties of the photolithographic process. With the structure of FIGS. 1-4, it is often desirable to form opening 20 as narrowly as possible so that features can be formed within a minimum perimeter.
FIG. 5 depicts an isometric view of a conventional flash memory device comprising a semiconductor wafer 12 having implanted source 50 and drain 52 regions with a channel region 53 between the source and drain regions. FIG. 5 further depicts transistor gate stacks 54 comprising gate (tunnel) oxide 56 formed under transistor floating gates 58, a capacitor dielectric layer 60 typically comprising a layer of silicon nitride interposed between two silicon dioxide layers, a word line (control gate) 62, and a silicon nitride capping layer 64. Prior to forming floating gates 58 and control gates 62, long, narrow trenches are etched into the wafer which extend across the wafer. A first portion 74 and a second portion 76 of a trench are depicted. The second trench portion 76 is filled with oxide 78 between adjacent drain regions 52. Oxide 80 also remains under the control gate 62. Spacers 82 are formed to electrically isolate the word line 62 from the floating gate 58.
FIGS. 6 and 7 are cross sections depicting a method used for forming the FIG. 5 structure. The cross sections of FIGS. 6 and 7 are generally taken along A-A of the completed structure of FIG. 5. FIG. 6 depicts semiconductor wafer 12, gate oxide 56, polysilicon floating gate layer 58, capacitor dielectric 60, and patterned photoresist layer 16. With this embodiment, the spacing between photoresist portions 16 is at the limit of optical lithography, typically about 0.08 microns. The capacitor dielectric 60, floating gate layer 58, and at least a portion of the gate oxide 56 are etched. The resist 16 is removed and a blanket spacer layer is formed then etched to result in spacers 82. Blanket layers of word line polysilicon and capping layers are formed and then patterned to result in the word line 62 and capping layer 64 as depicted in FIG. 7.
With the structure of FIGS. 5-7, it is desirable to form the floating gates along a word line as closely as possible. This allows the floating gates to be maximized to provide a maximum capacitive coupling between the floating gate and the control gate, and still provides a sufficient density of transistors. Trenches 74 are formed prior to forming the floating gates at a width corresponding to the distance between the floating gates, which is determined by the limits of optical lithography. The floating gates are formed in this direction during an etch of a blanket layer which separates the floating gate layer into a plurality of individual strips, and the individual floating gates are defined during the etch which defines the word lines.
A method for forming a semiconductor device which allows for the definition of features smaller than those available with the limitations of optical lithography would be desirable.